library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;

entity registrador_b is
	port(
      Lb_neg, CLK : in std_logic; -- neg significa negado (risco em cima)
      entrada_bw  : in std_logic_vector(7 downto 0);
	   saida_B     : out std_logic_vector(7 downto 0):="00000000"
	);
end registrador_b;

architecture arquitetura of registrador_b is
begin
	process (CLK,Lb_neg)
   begin
	   if (CLK'event and CLK='1') then
	      if(Lb_neg='0') then
		      saida_B<=entrada_bw;
   	   end if;
   	end if;
   end process;
end arquitetura; 
